NVIDIA
Senior DFT Engineer
$136K–$264K
US, CA, Santa Clara · Senior · Full-time · Posted Sep 30, 2026
- Experience
- BSEE (or equivalent experience) with 5+ years; MSEE with 3+ years; or PhD in DFT or related domains.
- Education
- BSEE (or equivalent experience), MSEE, or PhD in DFT or related domains.
About the job
Implements and validates design-for-test architectures and methodologies for NVIDIA’s next-generation semiconductor products.
What you'll do
- Implement test access mechanisms, IO BIST, memory BIST, and scan compression with cross-functional teams.
- Develop and deploy DFT methodologies for next-generation products.
- Mentor junior engineers on test designs and cost-quality trade-offs.
What they ask for
- BSEE (or equivalent experience) with 5+ years, MSEE with 3+ years, or a PhD in DFT or related domains.
- Knowledge of scan test plans, BIST for memories and IOs, fault modeling, ATPG, and fault simulation.
- Experience verifying and validating test patterns and logic on complex, multi-million-gate designs using vendor tools.
- Silicon debug and bring-up on ATE, including pattern formats, failure processing, and test program development.
Nice to have
- Strong programming and scripting skills in Perl, Python, or Tcl.
- Exposure to RTL and clock design, STA, place-n-route, and power.
Pay
136,000 USD - 218,500 USD (base salary, Level 3); 168,000 USD - 264,500 USD (base salary, Level 4)
Tools
Perl, Python, Tcl, ATPG, ATE, STA
Model-written summary · the original posting is authoritative