NVIDIA
Senior DFT Methodology Engineer
$168K–$310K
US, CA, Santa Clara · Senior · Full-time · Posted Oct 2, 2026
- Experience
- 10+ years of hands-on experience in SoC architecture, RTL design, and verification.
- Education
- BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain.
About the job
Architects and deploys design-for-test methodologies for next-generation silicon, supporting testability, debug, security, and post-silicon validation.
What you'll do
- Implement test access, memory BIST, memory dump, and DFX security methodologies, including RTL design, verification, and pattern generation.
- Coordinate with timing, physical design, software, bring-up, and production teams to balance cost and quality.
- Mentor junior engineers on test designs and trade-offs.
What they ask for
- BS/MS in Electrical or Computer Engineering, or equivalent experience, in a related domain, with proven DFT experience.
- 10+ years of hands-on experience in SoC architecture, RTL design, and verification.
- Experience using vendor tools to verify and validate test patterns and logic on complex, multi-million-gate designs; exposure to RTL and clocks design, STA, place-n-route, and power.
- Silicon debug and bring-up on ATE, with understanding of pattern formats, failure processing, and test program development.
Nice to have
- Knowledge of DFT security and hardware system security.
- Strong programming and scripting skills in Perl, Python, or Tcl.
Pay
168,000 USD - 264,500 USD (base salary, Level 4); 196,000 USD - 310,500 USD (base salary, Level 5)
Tools
RTL, STA, Perl, Python, Tcl, ATE, memory BIST, I1149.1
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