NVIDIA
Senior DFT Power Methodology Engineer
$168K–$310K
US, CA, Santa Clara · Senior · Full-time · Posted Oct 2, 2026
- Experience
- 12+ years with BSEE (or equivalent experience), 10+ years with MSEE, or 6+ years with PhD, in DFT design & power.
- Education
- BSEE (or equivalent experience), MSEE, or PhD.
About the job
Develop DFT power, thermal, and voltage-noise methodologies for manufacturing tests and next-generation products, using post-silicon analysis and AI/ML solutions to improve chip quality.
What you'll do
- Create low-power and thermal manufacturing-test solutions and develop DFT methodologies for next-generation products.
- Partner with Product Development and Power Architecture teams, and analyze post-silicon power data to guide future solutions.
- Mentor junior engineers on test design and trade-offs, including cost and quality.
What they ask for
- BSEE (or equivalent experience) with 12+ years, MSEE with 10+ years, or PhD with 6+ years of experience in DFT design & power.
- Understanding of fundamental DFT topics and VLSI power, timing, and voltage noise.
- Excellent knowledge of statistical tools for data analysis and insights.
- Good exposure to RTL & clocks design, STA, place-n-route, and power; experience in Silicon debug and bring-up on ATE or SLT platforms.
Nice to have
- Experience in Power Analysis, Thermal Analysis & IR Drop tools or applying AI to EDA-related problem-solving.
- Experience managing DFT Power Methodology or post-silicon debug for thermal & IR Drop.
Pay
168,000 USD - 264,500 USD (base salary, Level 4); 196,000 USD - 310,500 USD (base salary, Level 5)
Tools
DFT, Power Analysis, Thermal Analysis, IR Drop, RTL, STA, place-n-route, ATE or SLT
AI focus
Develop and deploy DFT methodologies using Applied ML & Gen AI solutions; apply AI to EDA-related problem-solving and use AI Coding harnesses.
Model-written summary · the original posting is authoritative