NVIDIA
Senior DFT - Silicon Validation Engineer
$168K–$310K
US, CA, Santa Clara · Senior · Full-time · Posted Oct 7, 2026
- Experience
- BSEE (or equivalent experience) with 8+ years, MSEE with 5+ years, or PhD with 3+ years in DFT or related domains.
- Education
- BSEE (or equivalent experience), MSEE, or PhD
About the job
Drive end-to-end DFT architecture and silicon validation for complex NVIDIA chips, from test strategy and ATE bring-up through debug, yield ramp, and production readiness.
What you'll do
- Collaborate across teams to define DFT architecture, methodologies, and ATE test strategies.
- Plan and perform early silicon validation on ATE; debug test content and analyze silicon behavior.
- Identify failure root causes and support yield ramp and production readiness.
What they ask for
- Expertise in silicon debug, bring-up, and productization of DFT features.
- Demonstrated leadership driving yield ramp and waste reduction for multiple products.
- Hands-on experience in pre-silicon validation for DFT features.
- Strong written and oral communication skills.
Nice to have
- Strong programming and scripting skills in Perl, Python, or Tcl.
- Experience implementing advanced DFT methodologies; knowledge of high-speed protocols, semiconductor process technology, or industry-standard DFT tools.
Pay
168,000 USD - 264,500 USD (base salary, Level 4); 196,000 USD - 310,500 USD (base salary, Level 5)
Tools
Perl, Python, Tcl, ATE
Model-written summary · the original posting is authoritative