Senior Full-Chip RTL Integration Engineer

What you'll do

• Lead RTL integration, including top-level connectivity, clocking, reset architecture, address mapping, and power-domain integration.
• Coordinate system-level integration and design closure with architecture, design, verification, DFT, and physical-design teams; perform RTL quality checks and support signoff.
• Develop integration-level verification plans, debug simulations, support coverage closure, and create automation to improve engineering productivity.

What they ask for

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience).
• Strong ASIC/SoC RTL integration experience and understanding of digital design, SoC architecture, clocking, reset, and bus protocols.
• Hands-on SystemVerilog and UVM verification experience, including ability to verify block-level and integration-level designs.
• Understanding of DFT methodologies and experience with lint, CDC, RDC, and design-quality signoff flows.

Nice to have

• Large-scale SoC or full-chip integration experience; exposure to Synopsys, Cadence, or Siemens DFT and verification tools.
• Low-power design and UPF experience; scripting in Python, Perl, Tcl, or Shell, including interest in automation and AI-assisted development tools.

Pay

168,000 USD - 264,500 USD base salary; 196,000 USD - 310,500 USD base salary

Tools

ASIC/SoC, SystemVerilog, UVM, Scan, ATPG, MBIST, LBIST, JTAG

AI focus

The role may use AI-assisted development tools to improve engineering productivity. NVIDIA also uses AI tools in its recruiting processes.