NVIDIA
Senior Logic Design Engineer, Cache Coherent Interconnects
$136K–$264K
US, CA, Santa Clara +1 · Senior · Full-time · Posted Mar 18, 2026
- Location
- US, CA, Santa Clara
US, OR, Hillsboro - Experience
- 5+ years.
- Education
- Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
About the job
Design and deliver CPU interconnect, coherency, and cache logic, from microarchitecture and RTL through synthesis, timing closure, verification, and implementation.
What you'll do
- Own and deliver a specific chip unit; write readable, high-performance, low-power RTL and design documentation.
- Perform synthesis and timing closure; collaborate with verification and implementation teams to meet timing, area, performance, and power goals.
- Assist with timing closure of super units.
What they ask for
- Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science, or equivalent experience.
- 5+ years of experience in processor or other related high performance semiconductor designs.
- Verilog expertise and deep understanding of ASIC design flow, including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
- Strong communication and interpersonal skills; strong background in computer architecture.
Nice to have
- Background in cache coherency or high speed interconnects.
- Track record of mentoring junior engineers and interns.
Pay
136,000 USD - 218,500 USD base salary (Level 3); 168,000 USD - 264,500 USD base salary (Level 4)
Tools
Verilog, RTL, ASIC, DFT, ECO
Model-written summary · the original posting is authoritative