Senior Memory Post Silicon Qualification Engineer

What you'll do

• Bring up and qualify GDDR, LPDDR, and HBM interfaces, including functional validation, IO tuning, and timing-margin analysis.
• Lead cross-team root-cause investigations and deliver reusable workarounds and productized fixes.
• Develop AI-enabled workflows for memory-data analysis, failure detection, and qualification decisions.

What they ask for

• B.Tech or M.Tech in Electrical, Electronics, or Computer Engineering, or equivalent experience.
• 10+ years in the semiconductor industry, including at least 3 years directly in memory-interface bring-up, characterization, and qualification on shipped silicon.
• Deep protocol and physical-layer knowledge of GDDR, LPDDR, or HBM, with an example of root-causing and productizing a fix for an ambiguous memory failure.
• Hands-on lab skills and working knowledge of PCB layout and SI/PI; demonstrated AI-driven workflow for memory characterization, margin analysis, or failure triage, adopted beyond personal use with measurable impact.

Nice to have

• Experience creating reusable qualification methodology, debug playbooks, or margin-analysis frameworks adopted by other teams.
• Team-deployed AI workflows such as agentic workflows, RAG-grounded debug assistants, automated shmoo analysis, or ML-driven margin prediction, with adoption metrics.

Pay

168,000 USD - 264,500 USD (base salary); 196,000 USD - 310,500 USD (base salary)

Tools

GDDR, LPDDR, HBM, oscilloscope, DMM, thermal chambers, protocol analyzers, PCB

AI focus

Build and deploy AI-enabled workflows for margin-data analysis, shmoo bucketing, failure-signature detection, workload-vs-margin correlation, and qualification decisions.