Drimva

NVIDIA

Senior Mixed Signal Circuit Design Engineer

$168K–$310K

US, CA, Santa Clara · Senior · Full-time · Posted Oct 12, 2026

Experience
4+ years of design experience in CMOS analog / mixed-signal circuit.
Education
MS in Electrical Engineering (or equivalent experience); PhD preferred.

About the job

Designs and implements high-speed mixed-signal interface circuits and analog circuits for next-generation NVLINK, taking designs from concept through silicon characterization and productization.

What you'll do

  • Design, simulate, verify, and implement high-speed interface and mixed-signal circuits, including transceivers and high-frequency PLLs.
  • Lead mask designers and mentor on floorplan and layout; support silicon lab characterization, bring-up, and debugging.
  • Collaborate with multifunctional teams to take designs through implementation and productizing.

What they ask for

  • MS in Electrical Engineering or equivalent experience; PhD preferred.
  • 4+ years of CMOS analog/mixed-signal circuit design experience.
  • Working knowledge of Cadence custom design tools, circuit simulator, and timing analysis tool; design experience in Data Converters, Tx, Rx, CDR, or PLL for high-speed IO interfaces.
  • In-depth understanding of deep submicron CMOS and related circuit design issues; experience in silicon bring-up, debugging, and lab instrumentation.

Nice to have

  • Knowledge of system level timing budget, signal integrity, and power integrity.
  • Experience in Verilog, Matlab, or Nanotime.

Pay

168,000 USD - 264,500 USD base salary (Level 4); 196,000 USD - 310,500 USD base salary (Level 5)

Tools

NVLINK, Cadence custom design tools, circuit simulator, timing analysis tool, CMOS, Verilog, Matlab, Nanotime

AI focus

The role designs high-speed interfaces and analog circuits for product lines that include artificial intelligence; NVIDIA also uses AI tools in its recruiting processes.

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 5, 2026 (UTC)