NVIDIA
Senior Performance Modeling Architect, CPU Fabric and LLC
$152K–$288K
US, CA, Santa Clara · Senior · Full-time · Posted May 6, 2026
- Experience
- 5+ years.
- Education
- Master’s or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience), focused on architecture.
About the job
Leads performance modeling and architectural analysis of CPU cache hierarchies and coherent interconnects for automotive and data center systems.
What you'll do
- Develop and maintain cycle-accurate models of coherent interconnects and shared caches.
- Analyze performance bottlenecks and evaluate coherency protocols, snooping filters, and architectural trade-offs using benchmarks.
- Collaborate with build, verification, and software teams to correlate models with silicon and optimize drivers.
What they ask for
- Master’s or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience), focused on architecture.
- Strong understanding of CPU microarchitecture, memory consistency models, and cache coherency protocols.
- Experience with C++ or SystemC for cycle-accurate or functional modeling.
- Proficiency in Python or similar scripting languages; understanding of NoC topologies, credit-based flow control, and arbitration logic.
Nice to have
- Automotive functional safety (ISO 26262) and data center PPA experience; PMU event experience.
- Formal verification, custom architectural exploration tools, or knowledge of CXL or HBM.
Pay
152,000 USD - 241,500 USD (base salary, Level 3); 184,000 USD - 287,500 USD (base salary, Level 4)
Tools
C++, SystemC, Python, SPEC, MLPerf, CHI, ACE, CXL
Model-written summary · the original posting is authoritative