NVIDIA
Senior Photonic Layout Design Engineer
$148K–$276K
US, CA, Santa Clara · Senior · Full-time · Posted Sep 8, 2026
- Experience
- At least 12+ years of hands-on, full-chip layout design experience.
- Education
- BS, MS, or Ph.D. in Electrical Engineering, Physics, or a closely related field (or equivalent experience).
About the job
Own physical design and verification of photonic integrated circuits, taking Silicon Photonics and SERDES designs from proof of concept through tape-out and manufacturing readiness.
What you'll do
- Lead manual and automated PIC layout, floor planning, waveguide routing, and mask data preparation.
- Perform post-layout DRC, LVS, fill, and density verification; resolve defects and layout issues before tape-out.
- Develop test structures, layout automation, custom Pcells, and AI-assisted design workflows.
What they ask for
- BS, MS, or Ph.D. in Electrical Engineering, Physics, or a closely related field (or equivalent experience).
- At least 12+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries.
- Deep understanding of analog circuit layout, Silicon Photonic constraints, and device physics within advanced sub-micron CMOS and SiPh technologies.
- Expertise with Cadence Virtuoso (Custom Layout, SDL) and verification suites; proficiency in programming or scripting languages for layout automation.
Pay
148,000 USD - 235,750 USD (base salary, Level 5); 176,000 USD - 276,000 USD (base salary, Level 6)
Tools
Cadence Virtuoso, Calibre, Hercules, ICV, Dracula, Primeyield, Python, SKILL
AI focus
Develop and implement AI-assisted design methods for layout automation and productivity; NVIDIA also uses AI tools in recruiting.
Model-written summary · the original posting is authoritative