NVIDIA
Senior Physical Design and Timing Engineer
$168K–$310K
US, MA, Westford · Senior · Full-time · Posted Oct 2, 2026
- Experience
- 8 years with a BS, or 4+ years with an MS, in Synthesis and Timing.
- Education
- BS in Electrical or Computer Engineering (or equivalent experience), or MS.
About the job
Drive physical design and timing for high-frequency, low-power DPUs and SoCs, optimizing performance, power, and area from RTL through implementation.
What you'll do
- Lead block-, chiplet-, and/or full-chip physical design and timing.
- Analyze and optimize design constraints and synthesis parameters to meet performance, power, and area targets.
- Support RTL-to-gds2 implementation, including synthesis, equivalence checking, floor-planning, timing and power convergence, and ECOs.
What they ask for
- BS in Electrical or Computer Engineering (or equivalent experience) with 8 years of Synthesis and Timing experience, or MS with 4+ years.
- Hands-on experience with full-chip/sub-chip Static Timing Analysis (STA), timing constraints, and timing convergence.
- Expertise in timing-path analysis and ECO fixes, including crosstalk and noise analysis, and in physical design optimization.
- Expertise with Synopsys PrimeTime or Cadence Tempus; proficiency in Python, Tcl, and Make.
Nice to have
- Experience with domain-specific STA and timing convergence for CPUs, GPUs, network processors, or SoCs.
- DFT timing closure, deep sub-micron process variation, or methodology, flow, and automation development experience.
Pay
168,000 USD - 264,500 USD base salary (Level 4); 196,000 USD - 310,500 USD base salary (Level 5)
Tools
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Make, RTL, gds2
AI focus
NVIDIA uses AI tools in its recruiting processes; the role itself does not state AI-related duties.
Model-written summary · the original posting is authoritative