Drimva

NVIDIA

Senior Physical Design Interposer Engineer

$168K–$310K

US, CA, Santa Clara +2 · Senior · Full-time · Posted Oct 2, 2026

Location
US, CA, Santa Clara
US, TX, Austin
US, CA, Remote
Experience
8 years of flow and methodology development experience.
Education
BS in Computer Science, Electrical Engineering, or a related field (or equivalent experience).

About the job

Build and maintain production-quality flows, tools, and methodologies that automate, analyze, and validate interposer designs and improve engineers’ workflows.

What you'll do

  • Design and develop VLSI flows and methodologies for interposer design.
  • Develop maintainable, easy-to-use applications and tools to construct, analyze, and validate interposer designs throughout production.
  • Optimize interposer designers’ daily workflows in collaboration with design engineers, package architects, and foundry partners.

What they ask for

  • BS in Computer Science, Electrical Engineering, or a related field (or equivalent experience).
  • 8 years of flow and methodology development experience building flows for interposer design used by engineering teams at scale.
  • Programming proficiency in Python and/or C++, including data structures, algorithms, object-oriented design, and code quality practices.
  • Demonstrated experience applying AI/ML techniques in engineering workflows and strong electrical-engineering fundamentals relevant to VLSI interposer design.

Nice to have

  • Understanding of VLSI package design, interposer design, and IC physical design.
  • Strong expertise in developing interposer design flows and methodologies.

Pay

168,000 USD - 264,500 USD (base salary, Level 4); 196,000 USD - 310,500 USD (base salary, Level 5)

Tools

Python, C++, AI/ML, LLMs, EDA

AI focus

Apply AI/ML in engineering workflows, such as using LLMs for code generation and debugging, building ML-assisted design analysis tools, or integrating AI-assisted flows into EDA environments.

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 4, 2026 (UTC)