NVIDIA
Senior Power Integrity Co-Design Engineer
$136K–$264K
US, CA, Santa Clara · Senior · Full-time · Posted Sep 23, 2026
- Experience
- 5+ years in silicon power integrity, voltage noise, or PDN.
- Education
- BS / MS / PhD in EE, CE, or related (or equivalent experience).
About the job
Architects and delivers voltage-noise and di/dt mitigation across silicon, package, board, and platform, from product targets through silicon validation and shipment.
What you'll do
- Own full-stack voltage-noise mitigation architecture and codesign trade-offs with engineering teams.
- Define and close product voltage-noise targets; build Sim-to-Si correlation methods and sign off results for shipment.
- Prototype reusable noise features, lead critical noise-bug resolution during bringup, and drive architecture-level trade-offs.
What they ask for
- BS / MS / PhD in EE, CE, or related (or equivalent experience).
- 5+ years in silicon power integrity, voltage noise, or PDN.
- Deep expertise in at least one listed area, such as di/dt analysis and mitigation, voltage droop, PDN design, transient noise, decap budgeting, or voltage regulator response.
- Hands-on silicon bringup, characterization, and correlation experience.
Nice to have
- Patents or publications in power integrity, voltage noise, PDN, or di/dt mitigation.
- ML/AI applied to noise modeling, transient prediction, droop response, or feature optimization.
Pay
136,000 USD - 218,500 USD (base salary, Level 3); 168,000 USD - 264,500 USD (base salary, Level 4)
Tools
silicon, package, board, platform, scopes, probes, DAQ, simulator
AI focus
AI/ML application to noise modeling, transient prediction, droop response, or feature optimization is a preferred area; the team is rebuilding its toolchain around AI.
Model-written summary · the original posting is authoritative