NVIDIA
Senior Signal and Power Integrity Engineer
$136K–$264K
US, CA, Santa Clara · Senior · Full-time · Posted Aug 17, 2026
- Experience
- Minimum 4 years as a SI/PI engineer.
- Education
- BS/MS in Electrical Engineering (or equivalent experience).
About the job
Leads board- and system-level signal and power integrity design, simulation, analysis, and measurement for high-speed interfaces and customer board designs.
What you'll do
- Lead board/system SI design, including PCB stack-up, material selection, design guides, layout review, and post-layout analysis.
- Simulate high-speed interfaces and analyze and optimize PCB power delivery networks.
- Collaborate with Package, PCB Design, and Application Engineering teams; perform TDR and VNA measurements for material characterization and model correlation.
What they ask for
- BS/MS in Electrical Engineering (or equivalent experience).
- Minimum 4 years of experience as a SI/PI engineer.
- Understanding of electromagnetics, channel components, transmission line theory, and high-volume PCB manufacturing impacts on signal integrity.
- Experience with high-speed electrical interfaces, HFSS, Sigrity, Hspice or similar simulation tools, and Cadence Allegro PCB designer and Constraints Manager or other PCB stack-up designer tools.
Nice to have
- Expertise in high-speed interface SI/PI design; exposure to package design, interface timing budgets, or system modeling.
- Familiarity with transmitter/receiver design, equalization schemes, or NRZ and PAM4 signaling.
Pay
136,000 USD - 218,500 USD (base salary, Level 3); 168,000 USD - 264,500 USD (base salary, Level 4)
Tools
PCIE, LPDDR/DDR/GDDR, MIPI, HDMI, USB, HFSS, Sigrity, Hspice
Model-written summary · the original posting is authoritative