NVIDIA
Senior Signal Integrity Engineer – LPU Packaging
$168K–$310K
US, CA, Santa Clara · Senior · Full-time · Posted Sep 2, 2026
- Experience
- 8+ years of industry experience in signal integrity, high-speed interconnect design, or related hardware development roles.
- Education
- BS, MS, or PhD in Electrical Engineering or equivalent experience.
About the job
Leads signal integrity design, simulation, measurement correlation, and optimization of high-speed SerDes channels for advanced packages and data center systems.
What you'll do
- Lead SI design and analysis across die, package, board, and other channel interfaces; develop simulation and co-simulation methods.
- Perform pre- and post-layout analysis, review layouts, and create design guidelines for electrical performance.
- Correlate simulations with lab measurements, support bring-up and debug, and automate reusable SI analysis flows.
What they ask for
- BS, MS, or PhD in Electrical Engineering or equivalent experience.
- Strong background in electromagnetics, transmission line theory, channel modeling, and high-speed serial links.
- Experience with high-speed SerDes design and analysis for advanced packaging and/or large-scale systems.
- Hands-on experience with industry-standard SI tools; channel models, S-parameters, and IBIS-AMI flows; and simulation-to-measurement correlation.
Nice to have
- Experience with package and system SI for PCIe, CXL, NVLink, Ethernet, or other high-speed interfaces.
- Experience with advanced packaging, HPC/data center/AI platforms, or SI signoff and automation methods.
Pay
168,000 USD - 264,500 USD (base salary, Level 4); 196,000 USD - 310,500 USD (base salary, Level 5)
Tools
Ansys HFSS, SIwave, Cadence Sigrity, ADS, HSPICE, IBIS-AMI, VNA, TDR
Model-written summary · the original posting is authoritative