NVIDIA
Senior Silicon Architect – Cache Coherent Interconnects
$168K–$310K
US, CA, Santa Clara +2 · Senior · Full-time · Posted Oct 30, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin
US, OR, Hillsboro - Experience
- 8+ years.
- Education
- Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
About the job
Own silicon architecture and construction planning for next-generation CPU processors, including dielet partitioning, floorplanning, packaging, and die-to-die interfaces.
What you'll do
- Explore 2D, 2.5D, and 3D dielet constructions and placement of IO and compute across dielets.
- Develop early floorplans and plan die-to-die and off-chip IO, including UCIe, DRAM, and PCIe.
- Coordinate with architecture, logic design, physical design, and packaging teams to meet area, performance, power, and thermal goals.
What they ask for
- Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
- 8+ years of experience in processor or other related high-performance semiconductor designs.
- Deep understanding of digital design, CPU system architecture, and ASIC floor-planning, including wire densities on-die and across 3D connected dies.
- Strong communication and interpersonal skills, with the ability to work in a dynamic, global team.
Nice to have
- Background in cache coherency or high-speed interconnects and industry-standard coherency/IO/memory protocols.
- Knowledge of advanced packaging, through-silicon via configurations, backside power delivery, and dielet, interposer, and substrate connectivity.
Pay
168,000 USD – 264,500 USD (base salary); 196,000 USD – 310,500 USD (base salary)
Tools
UCIe, DRAM, PCIe, TSMC InFO, CoWoS, Intel EMIB
Model-written summary · the original posting is authoritative