Senior Silicon Circuit Co-Design Engineer

What you'll do

• Own circuit co-design, bring-up, and post-silicon validation across PVT through production sign-off; correlate measurements with pre-silicon predictions and investigate failures.
• Build AI agents, automation, and analysis tools for test orchestration, data pipelines, and circuit analysis.
• Use characterization data to inform binning, guard-banding, reliability sign-off, and design improvements; lead and mentor engineers.

What they ask for

• BS or MS in Electrical Engineering, Computer Engineering, or equivalent experience in the lab.
• 8+ years of hands-on silicon bring-up, frequency and power characterization, or post-silicon validation on real hardware.
• Strong analog, digital, and mixed-signal circuit fundamentals, hands-on lab skills, and tester-to-system correlation experience.
• Depth in binning, PVT analysis, guard-banding, and optimization trade-offs; scripting proficiency in Python, C/C++, or equivalent.

Nice to have

• Built co-design or correlation methodologies adopted by other teams, or traced silicon anomalies through resolution.
• Built or deployed AI-driven analysis or failure-triage flows; experience with datacenter-scale or high-performance silicon.

Pay

168,000 USD - 264,500 USD (base salary)

Tools

Python, C/C++, oscilloscopes, multimeters, DAQs, spectrum analyzers, silicon debug tools

AI focus

Own and build AI agents for automated test orchestration, intelligent data pipelines, and analysis flows; assess where AI helps and where it introduces risk. NVIDIA also uses AI tools in recruiting.