NVIDIA
Senior Software R&D Engineer, ECO Route - VLSI EDA
$168K–$310K
US, CA, Santa Clara +1 · Senior · Full-time · Posted Aug 31, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin - Experience
- 5+ years of relevant experience.
- Education
- MS, PhD, or equivalent experience.
About the job
Develops and deploys algorithms and software for ECO routing and physical optimization in VLSI design, enabling high-performance hardware designs.
What you'll do
- Develop incremental physical-design technology for DRC- and parasitic-aware logic changes, including all-layer and metal-only ECOs.
- Invent detailed-routing algorithms and cross-domain optimization tools spanning logic, timing, clocks, testability, power, placement, routing, and DRCs.
- Own algorithm development through implementation, validation, and production deployment.
What they ask for
- Strong expertise in C++, high-performance software architecture, and algorithm development, including complexity, data structures, and memory efficiency.
- Deep understanding of detailed routing, including advanced design rules, pin access, route optimization, and DRC-aware implementation.
- Understanding of clock distribution, DFT, and power delivery.
- Authorization to work on export controlled data arising in CPUs, GPUs, LPUs, and communication networks.
Nice to have
- Familiarity with logic and physical co-optimization, including logic restructuring, technology mapping, and SAT solvers.
- Experience in placement, legalization, IR drop reduction, or applying machine-learning techniques to physical design, combinatorial optimization, or algorithm-performance tuning.
Pay
168,000 USD - 264,500 USD base salary for Level 4; 196,000 USD - 310,500 USD base salary for Level 5
Tools
C++, SAT solvers, LLMs, reinforcement learning, GNNs
AI focus
The role may apply LLMs, reinforcement learning, GNNs, or other machine-learning techniques to physical design, combinatorial optimization, or algorithm-performance tuning.
Model-written summary · the original posting is authoritative