NVIDIA
Senior STA Signoff Methodology Engineer
$168K–$310K
US, CA, Santa Clara +1 · Senior · Full-time · Posted Aug 20, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin - Experience
- 8 years of experience in ASIC design and timing.
- Education
- MS in Electrical or Computer Engineering, or equivalent experience.
About the job
Develops and improves timing-signoff methodologies for advanced NVIDIA chips, using simulations, analysis, and automation to enhance performance, predictability, and reliability.
What you'll do
- Run large-scale SPICE simulations and STA experiments to model advanced-technology effects on chip timing.
- Develop STA and PNR flows, tools, and recommendations for advanced-node physical effects and timing signoff.
- Analyze data to improve STA-to-silicon correlation and collaborate on timing-signoff strategies.
What they ask for
- MS in Electrical or Computer Engineering, or equivalent experience.
- Solid understanding of RC extraction, device physics, STA methodologies, EDA-tool limitations, and the mathematics and physics underlying electrical design.
- Experience with low-power techniques and understanding of signal and power integrity, timing margins, and standard-cell, memory, and I/O IP modeling.
- Hands-on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, and beyond; familiarity with industry-standard ASIC tools.
Nice to have
- Familiarity with 3D IC integration, die stacking and packaging, and their timing-closure impacts.
- Strong data-analysis and modeling skills using Python, JMP, or similar platforms; proficiency in Tcl and Python, with C++ experience a plus.
Pay
168,000 USD - 264,500 USD (base salary, Level 4); 196,000 USD - 310,500 USD (base salary, Level 5)
Tools
SPICE, STA, PNR, Python, JMP, PrimeTime, ICC2, RedHawk
AI focus
The role contributes to chips and platforms supporting AI computing; NVIDIA also states that it uses AI tools in its recruiting processes.
Model-written summary · the original posting is authoritative