Senior System Integration and Validation Engineer

What you'll do

• Own end-to-end system validation, including feature checks, PVT stress, system-stress campaigns, and multi-unit fleet testing.
• Lead complex silicon, board, and software debug through root-cause analysis and productized fixes; coordinate cross-functional crisis response.
• Develop automated test coverage and deploy guarded AI-enabled debug and validation workflows with measurable impact.

What they ask for

• BTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering, or equivalent experience.
• 8+ years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products.
• Hands-on debug across silicon, board, and software boundaries, including logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior.
• Demonstrated leadership in resolving ambiguous multi-team failures and building or scaling AI-driven validation workflows with adoption and measurable impact.

Nice to have

• Reusable validation methodologies, debug playbooks, or test frameworks adopted by other teams, supported by recognized contributions.
• Subsystem depth in HBM, SerDes or high-speed I/O, power and thermal, or advanced packaging; or experience partnering across global engineering hubs.

Pay

168,000 USD - 264,500 USD (base salary, Level 4); 196,000 USD - 310,500 USD (base salary, Level 5)

Tools

GPU, SoC, PVT, HBM, SerDes, RAG

AI focus

Build and deploy AI-enabled debug, triage, root-cause hypothesis generation, and regression workflows with evaluations, guardrails, and measurable team-level impact.