NVIDIA
Senior System Integration Engineer, Memory
$196K–$310K
US, CA, Santa Clara +4 · Senior · Full-time · Posted Sep 23, 2026
- Location
- US, CA, Santa Clara
US, TX, Remote
US, WA, Remote
US, ID, Remote
US, CA, Remote - Experience
- 12+ years.
- Education
- BS or MS in EE/CE, or equivalent experience.
About the job
Own end-to-end HBM and LPDDR integration, bringup, characterization, debug, and closure for next-generation SoCs, from first silicon through production.
What you'll do
- Integrate, bring up, characterize, and debug HBM and LPDDR memory subsystems.
- Drive memory performance, power, thermal, reliability, margining, and stability closure across silicon, package, board, and firmware.
- Plan validation and characterization, track issues, and establish operating points and release criteria.
What they ask for
- BS or MS in EE/CE, or equivalent experience.
- 12+ years in HBM, LPDDR, or high-speed memory systems, including hands-on silicon bringup, characterization, and debug at scale.
- Deep command of SI/PI, timing, margining, and memory training; ability to work across design, package, firmware, validation, and product teams.
Nice to have
- PHY controller development experience.
- HBM3/HBM3E specifics, JEDEC margins, thermal-electrical co-sim, ECC methodology, and power management.
Pay
196,000 USD - 310,500 USD (base salary)
Tools
HBM, LPDDR, VF shmoo, SI/PI, HBM3/HBM3E, LLM-assisted tools, ML models
AI focus
Use LLM-assisted tools and ML models for failure-signature analysis, root-cause investigation, and outlier detection; automate characterization data collection, test sequencing, and results analysis; use LLMs for architecture exploration, spec navigation, and trade-off analysis.
Model-written summary · the original posting is authoritative