Drimva

NVIDIA

Senior Systems Performance Engineer

$136K–$259K

US, CA, Santa Clara +1 · Senior · Full-time · Posted Oct 28, 2026

Location
US, CA, Santa Clara
US, TX, Austin
Experience
5+ years of relevant experience in systems performance engineering, performance modeling, accelerated computing, or complex system development and debug.
Education
BS in Computer Engineering, Electrical Engineering, Computer Science, or a related field, or equivalent experience.

About the job

Develop and validate automated workloads, performance models, and test strategies for GPU-accelerated server products.

What you'll do

  • Develop and tune GPU and AI workloads to stress hardware subsystems and expand validation coverage.
  • Model and analyze system performance, design experiments, and investigate workload or hardware/software failures.
  • Build automation for workload deployment, experiment execution, telemetry collection, and analysis.

What they ask for

  • Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field, or equivalent experience.
  • Deep understanding of computer architecture, including GPU and CPU execution, memory hierarchies, and interconnects.
  • Experience developing performance models and validating predictions against system measurements.
  • Hands-on AI workload profiling and tuning, strong Python and data analysis skills, and working knowledge of CUDA and GPU profiling tools.

Nice to have

  • Experience with NVIDIA Dynamo, TensorRT-LLM, vLLM, SGLang, or NCCL.
  • CUDA kernel development or optimization using cuBLAS, CUTLASS, or related libraries.

Pay

136,000 USD - 212,750 USD base salary (Level 3); 168,000 USD - 258,750 USD base salary (Level 4)

Tools

CUDA, PyTorch, TensorRT-LLM, vLLM, SGLang, Python, Linux, NVIDIA Dynamo

AI focus

Onboard, profile, tune, and validate AI training and inference workloads on new GPU platforms.

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 4, 2026 (UTC)