Senior Verification Engineer

What you'll do

• Define verification scope, develop functional and performance testplans, build scalable UVM infrastructure, and drive coverage closure.
• Develop testbenches and checkers; debug reference models, HLS designs, and complex integration issues across teams and partners.
• Collaborate with architects and ASIC engineers on design solutions and deploy consistent verification flows.

What they ask for

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent experience).
• Strong hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++; experience with constrained-random stimulus, functional coverage, assertion-based verification, and C/C++-based testbenches.
• Proficiency with VCS, Verdi/Debussy, and GDB, plus software engineering practices including version control and code review.
• Domain knowledge of display pipelines, protocols, MMU interaction with ISO clients, and system low-power features.

Nice to have

• Prior Display Unit Verification experience, including pixel processing, ISO performance testing, and HLS-based designs.
• Experience verifying display protocols end-to-end, MMU/SMMU behavior under ISO traffic, low-power sequences, or shaping architectural specifications and micro-architecture decisions.

Pay

168,000 USD - 264,500 USD base salary; 196,000 USD - 310,500 USD base salary

Tools

UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi/Debussy, GDB

AI focus

Use agentic AI to automate repetitive tasks, accelerate debug, and improve engineering efficiency.