NVIDIA
Software R&D Engineer, RTL Optimization Tools
$136K–$218K
US, CA, Santa Clara +1 · Full-time · Posted Jun 11, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin - Experience
- 3+ years of relevant experience in CAD software and VLSI hardware design.
- Education
- MS or PhD in Electrical Engineering or Computer Science or equivalent experience
About the job
Develops internal EDA software and algorithms to analyze and optimize RTL for quality, timing, and power, and helps deploy these tools within hardware design teams.
What you'll do
- Invent parallel, graph-based methods for RTL traversal, analysis, and manipulation.
- Analyze how RTL changes affect latency, power, DFT, clocking, and power delivery.
- Explore AI and algorithmic methods for suggesting or implementing RTL changes and improving logic synthesis.
What they ask for
- MS or PhD in Electrical Engineering or Computer Science, or equivalent experience.
- 3+ years of relevant experience in CAD software and VLSI hardware design.
- C++ software development, particularly algorithms for graph traversal, pattern matching, and optimization.
- Familiarity with RTL design, Verilog and SystemVerilog, hardware design concerns, and EDA techniques.
Nice to have
- Experience with EDA building blocks such as Verific and Espresso.
- Experience in high-performance software, combined software and hardware roles, or machine learning techniques.
Pay
136,000 USD - 218,500 USD (base salary)
Tools
C++, Verilog, SystemVerilog, Verific, Espresso, SAT solvers, LLMs, GNNs
AI focus
Explores LLMs, GNNs, GANs, and Reinforcement Learning to suggest or automatically implement RTL modifications; also explores machine learning for analysis, optimization, and code generation.
Model-written summary · the original posting is authoritative