NVIDIA
SRAM Circuit Design Engineer - New College Grad 2026
$116K–$218K
US, CA, Santa Clara · Full-time · Posted Oct 13, 2026
- Experience
- SRAM design experience required; no years specified.
- Education
- Master's degree or higher in Electrical Engineering or a related field (or equivalent experience).
About the job
Designs and validates embedded SRAM macros and develops SRAM compiler automation for NVIDIA chips, while supporting SOC design, silicon testing, and productization.
What you'll do
- Design, verify, debug, and oversee layout implementation of transistor-level SRAM macros.
- Develop automation to assemble and validate multiple SRAM macros; explore future process nodes and optimize power, performance, and area.
- Collaborate with SOC design partners and guide silicon test, characterization, and productization efforts.
What they ask for
- Master's degree or higher in Electrical Engineering or a related field (or equivalent experience).
- SRAM design experience and a strong background in digital circuit design, layout, and validation on advanced FinFET and nanosheet processes.
- Experience designing single-port, dual-port, or register-file SRAM macros, including self-timed logic and sense amplifiers.
- Familiarity with Cadence Virtuoso schematic and layout capture tools; demonstrated delivery of silicon IP into production.
Nice to have
- Skills in AI coding and analysis tools such as Codex and Claude Code.
- Silicon testing/debug experience; written, verbal, and presentation skills.
Pay
116,000 USD - 189,750 USD (base salary, Level 2); 136,000 USD - 218,500 USD (base salary, Level 3)
Tools
Cadence Virtuoso, Codex, Claude Code, FinFET, nanosheet
AI focus
Develops SRAM compiler automation using NVIDIA's compute resources; preferred use of AI coding and analysis tools such as Codex and Claude Code. NVIDIA also states it uses AI tools in recruiting.
Model-written summary · the original posting is authoritative