System Verification Co-Design Engineer - Speed and Rel

What you'll do

• Co-design system-level speed features and optimize speed-reliability margins with cross-functional teams.
• Develop verification methods, bring-up flows, and automation for pre- and post-silicon characterization and validation.
• Lead complex silicon and system-level debug, correlating silicon behavior with simulation and design expectations.

What they ask for

• MS in EE, CE, Systems Engineering, or equivalent experience.
• 4+ years of experience in a related hardware engineering role.
• Hands-on experience with silicon bring-up, frequency and power characterization, PPA analysis, system/platform understanding, tester-to-system correlation, and lab instrumentation.
• Scripting proficiency in Python and/or Perl; comfortable in Windows, Linux, and Android; familiarity with statistical methods and data analysis tools (JMP or equivalent); demonstrated use of AI or LLM-based tools in an engineering workflow.

Nice to have

• Background in gaming, automotive, or datacenter segments.
• Experience building or deploying AI-assisted characterization, log analysis, or debug automation in a production silicon environment; familiarity with LLM evaluation, prompt engineering, or agentic scripting pipelines.

Pay

136,000 USD - 218,500 USD (base salary, Level 3); 168,000 USD - 264,500 USD (base salary, Level 4)

Tools

Python, Perl, Windows, Linux, Android, JMP, Claude, Copilot

AI focus

Uses AI and LLM-assisted engineering workflows for scripting acceleration, log triage and analysis, pattern detection, and characterization/debug automation; requires validating outputs and assessing automation risks.