NVIDIA
VLSI CAD Timing Intern, Applied AI - Summer 2027
US, CA, Santa Clara · Internship · Posted Oct 29, 2026
- Education
- Currently pursuing a Master’s or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Develop AI-assisted tools and workflows for timing and constraint analysis in advanced ASIC designs, supporting engineers in achieving predictable timing closure.
What you'll do
- Support static timing analysis flows and automate timing, constraints, and QoR validation.
- Analyze timing reports, constraints, and design data across corners and modes; collaborate on timing sign-off strategies.
- Contribute to AI- or analytics-assisted timing analysis, constraint checking, and flow optimization.
What they ask for
- Currently pursuing a Master’s or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Coursework or academic knowledge in VLSI/ASIC design, digital circuits, or computer architecture.
- Exposure to applying agentic AI to back-end VLSI tasks.
- Familiarity with static timing analysis, constraints, or digital design flows; scripting or programming knowledge, with Python preferred.
Nice to have
- Academic projects, research, or internships related to VLSI, physical design, STA, or EDA tools; exposure to TCL.
- Exposure to machine learning, data analysis, or AI applied to engineering; workflow automation or large-dataset analysis experience.
Pay
20 USD - 71 USD per hour; hourly rate
Tools
PrimeTime, Tempus, Python, TCL
AI focus
Develop and apply AI-assisted approaches, including agentic automation, to timing analysis, constraint checking, flow optimization, and related back-end VLSI workflows.
Model-written summary · the original posting is authoritative