OLIX
Senior/Staff Design for Test Engineer
$321K
Austin, TX +1 · On-site · Staff · Full-time · Posted May 27, 2026
- Location
- Austin, TX
Bristol, UK - Experience
- 7+ years; hands-on DFT architecture, implementation, and verification for high-performance ASICs or SoCs.
- Visa sponsorship
- Eligibility to work depends on most recent citizenship or permanent residency status. Applicants whose most recent citizenship or permanent residency is in listed restricted countries are generally not considered; subsequent citizenship or permanent residency in an unrestricted country may permit eligibility.
About the job
Own end-to-end DFT strategy and implementation for OLIX’s high-performance accelerator silicon, from test architecture and verification through pattern generation and silicon bring-up.
What you'll do
- Architect, implement, and verify DFT features and test strategies for complex ASIC designs.
- Develop and optimize ATE-compatible test patterns to improve fault coverage and manufacturing yield.
- Collaborate across engineering teams on DFT interfaces, test control, PPA, and silicon debug; mentor junior engineers.
What they ask for
- 7+ years of hands-on DFT architecture, implementation, and verification for high-performance ASICs or SoCs, including ownership of at least one product with comprehensive DFT coverage.
- Experience implementing and verifying advanced DFT features, such as Scan/ATPG, Boundary Scan, and Memory BIST/Repair.
- Expertise in industry-standard DFT EDA flows, including scan insertion, ATPG, pattern simulation, fault modeling, and diagnosis.
- Proficiency with DFT flows and Python/Tcl scripting for automation, pattern management, and silicon debug/bring-up.
Nice to have
- Tape-out experience at 22 nm or below.
- Knowledge of high-speed SerDes or HBM/DDR DFT challenges, AI/ML workloads, or open-source DFT tools.
Pay
$321K (currency not stated; compensation type not specified)
Tools
Scan, JTAG, Boundary Scan, Memory BIST, SystemVerilog, Verilog, VHDL, Python/Tcl
AI focus
Develop DFT architectures and test methods for next-generation AI accelerator hardware.
Model-written summary · the original posting is authoritative