Palo Alto Networks
Senior ASIC Design Verification Engineer
$129K–$209K
Santa Clara, United States of America · No · Senior · Full-time · Posted Oct 20, 2026
- Experience
- Minimum 5 years in ASIC design verification; demonstrated success taking multiple ASIC products from concept to mass production.
- Education
- BS in EE, CE, or CS, or equivalent military experience; MSEE preferred.
- Visa sponsorship
- Will not sponsor applicants for work visas for this position.
About the job
Verifies ASICs for next-generation firewall products across simulation, emulation, formal verification, and silicon validation to ensure they meet feature, performance, and reliability requirements.
What you'll do
- Define verification methodologies, test plans, coverage, and scalable test benches; write tests and debug failures.
- Plan and run coverage-driven, constrained-random simulation and develop emulation flows, tests, and infrastructure.
- Build Python automation for triage, coverage closure, metrics, and verification tasks.
What they ask for
- BS in EE, CE, or CS, or equivalent military experience.
- Minimum 5 years experience in ASIC design verification.
- Demonstrated success taking multiple ASIC products from concept to mass production.
- Expertise in SystemVerilog and UVM; strength in test planning, functional coverage, scalable test benches, self-checking infrastructure, constrained-random tests, debugging, and coverage closure.
Nice to have
- MSEE.
- Experience in networking and cyber security, formal property verification, silicon validation, or creating models in Python and C/C++.
Pay
$129,200.00 - $209,000.00/yr (USD; annual base salary)
Tools
SystemVerilog, UVM, Python, C/C++, Perl, UNIX shell
AI focus
Integrate modern AI tools, such as LLM coding assistants, automated test generators, or ML-enhanced EDA features, into hardware design, scripting, or verification workflows.
Model-written summary · the original posting is authoritative