Palo Alto Networks
Sr FPGA Design Engineer (NetSec)
$156K–$253K
Office - USA - CA - Headquarters · No · Senior · Full-time · Posted Oct 29, 2026
- Experience
- 5+ years FPGA/CPLD development experience.
- Education
- BS in EE, CE, or CS; MSEE or equivalent military experience preferred.
- Visa sponsorship
- Immigration sponsorship: Yes.
About the job
Design and validate FPGA, CFPGA, and CPLD logic and hardware acceleration platforms for next-generation firewalls, from architecture through lab bring-up.
What you'll do
- Develop specifications and SystemVerilog/Verilog RTL, then synthesize, implement, and close timing on FPGA designs.
- Prototype and validate ASIC designs on FPGA platforms, including lab bring-up and in-system debugging.
- Integrate high-speed IP and collaborate with software teams on interfaces, memory maps, and AI-enabled design or verification workflows.
What they ask for
- BS in EE, CE, or CS.
- 5+ years FPGA/CPLD development experience.
- Expert SystemVerilog and Verilog RTL skills; experience with simulation tools such as VCS or Questa.
- Experience with FPGA synthesis, placement, routing, multi-clock static timing closure, scripting, high-speed IP integration, and FPGA lab validation.
Nice to have
- MSEE or equivalent military experience.
- ASIC-to-FPGA prototyping, high-density FPGA platforms, formal verification, or networking and board-management logic experience.
Pay
$156,400.00 - $253,000.00 USD/year, base salary
Tools
SystemVerilog, Verilog, Vivado, Quartus, Synopsys, VCS, Questa, Python
AI focus
Integrate modern AI tools into hardware design, scripting, or verification workflows, and pilot AI-driven design or verification flows to reduce schedule risk.
Model-written summary · the original posting is authoritative