Positron
ASIC Design Engineer
$225K–$350K
Austin, TX · On-site · Full-time · Posted Aug 2, 2026
- Experience
- 8+ years of ASIC/SoC RTL design experience.
- Education
- BS/MS in EE/CE (or related).
About the job
Leads the microarchitecture, RTL design, integration, and signoff of IP blocks and subsystems for AI inference ASICs/SoCs, owning PPA outcomes and guiding cross-functional work.
What you'll do
- Define microarchitecture and deliver production-quality, parameterized SystemVerilog RTL; lead design reviews and mentor junior engineers.
- Lead lint, CDC/RDC, DFT integration, synthesis bring-up, and PPA optimization in collaboration with physical design.
- Architect and integrate interconnects, DMA, coherency logic, and HBM/DDR interfaces; contribute automation and support post-silicon debug.
What they ask for
- BS/MS in EE/CE or related field.
- 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
- Proven leadership delivering designs from specification through microarchitecture, RTL, and signoff, with strong PPA outcomes.
- Deep SystemVerilog expertise and extensive front-end flow/tool experience; hands-on expertise in at least three specified interface, memory, or datapath areas.
Nice to have
- AI/ML accelerator design background.
- Formal verification/SVA, low-power design, cocotb/UVM, RISC-V, coherence protocols, or COT flow experience.
Pay
$225,000 – $350,000 USD base salary
Tools
SystemVerilog, AXI, CHI, ACE, HBM, DDR, Python, Tcl
AI focus
Designs IP blocks and subsystems for AI inference ASICs/SoCs; preferred experience includes AI/ML accelerator design.
Model-written summary · the original posting is authoritative