Positron
ASIC Design Engineer, Principal
$225K–$350K
Austin, TX · On-site · Principal · Full-time · Posted Aug 2, 2026
- Experience
- 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
- Education
- BS/MS in EE/CE (or related).
About the job
Leads the microarchitecture, RTL design, integration, and signoff of IP blocks and subsystems for AI inference ASICs and SoCs, while mentoring engineers and driving performance, power, and area goals.
What you'll do
- Define microarchitecture and deliver production-quality SystemVerilog RTL for complex IP and subsystems.
- Lead design signoff activities, own block PPA, and integrate interconnect, DMA, coherence, and memory interfaces.
- Set design methodologies, collaborate across teams, and mentor engineers through reviews and technical decisions.
What they ask for
- BS/MS in EE/CE or related field.
- Proven experience leading designs from specification through microarchitecture, RTL, and signoff with strong PPA outcomes.
- Deep SystemVerilog RTL expertise and extensive experience with front-end flows/tools, including lint, CDC, synthesis/STA, and DFT.
- Hands-on expertise in at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, or high-throughput datapaths.
Nice to have
- Background in AI/ML accelerator design.
- Formal verification/SVA expertise; low-power design, cocotb/UVM, RISC-V, coherence protocols, or COT flows.
Pay
$225,000 – $350,000 USD base salary
Tools
SystemVerilog, AXI, CHI, ACE, HBM, DDR, Python, Tcl
AI focus
Designs IP blocks and subsystems for AI inference ASICs/SoCs; preferred background includes AI/ML accelerator design.
Model-written summary · the original posting is authoritative