Positron
ASIC Design Engineer, Senior
$200K–$300K
Remote (United States) · Remote · Senior · Full-time · Posted Sep 29, 2026
- Experience
- 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
- Education
- BS/MS in EE/CE (or related).
About the job
Leads microarchitecture and SystemVerilog RTL design, integration, and signoff for IP blocks and subsystems in AI inference ASICs/SoCs.
What you'll do
- Define microarchitecture and deliver production-quality RTL; own block PPA and drive optimizations through signoff.
- Lead front-end signoff and integration, including lint, CDC/RDC, DFT, synthesis bring-up, and collaboration on floorplan and timing closure.
- Develop design methodologies and automation, collaborate across teams, and mentor engineers.
What they ask for
- BS/MS in EE/CE or related field.
- Proven record leading complex silicon designs from specification through RTL and signoff with strong PPA outcomes.
- Deep SystemVerilog RTL expertise and extensive front-end flow/tool experience, including lint, CDC, synthesis/STA, and DFT.
- Hands-on expertise in at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, and high-throughput datapaths.
Nice to have
- AI/ML accelerator design background.
- Formal verification/SVA, low-power design, cocotb/UVM collaboration, or familiarity with RISC-V, coherence protocols, or COT flows.
Pay
$200,000 – $300,000 USD base salary
Tools
SystemVerilog, AXI, CHI, ACE, HBM, DDR, Python, Tcl
AI focus
Designs IP blocks and subsystems for AI inference ASICs/SoCs.
Model-written summary · the original posting is authoritative