ASIC Physical Design Engineer - DFT, Senior

What you'll do

• Architect and implement DFT features, integrate internal and third-party DFT IP, and work directly in RTL, synthesis, and DFT flows.
• Develop and execute DFT verification and ATPG strategies to meet coverage targets before tapeout.
• Partner with backend and cross-functional teams on physical implementation, test architecture, and silicon bring-up.

What they ask for

• BS, MS, or PhD in Electrical Engineering or Computer Engineering.
• Extensive hands-on DFT implementation on complex SoCs, including multiple successful production tapeouts.
• Required hands-on experience with Siemens Tessent DFT solutions (SSN, EDT, MBIST, RTLpro, Scanpro, Tessent Diagnosis).
• Strong RTL skills using Verilog/SystemVerilog; practical synthesis and gate-level verification experience; scripting ability in Python, Tcl, Perl, or similar.

Nice to have

• Experience with high-performance AI accelerators, GPUs, CPUs, networking ASICs, PCIe, HBM, LPDDR, or chiplet architectures.
• Exposure to SerDes, advanced process nodes (5nm and below), low-power design, yield enhancement, manufacturing test, or silicon bring-up.

Pay

$200,000 – $300,000 USD base salary

Tools

Verilog/SystemVerilog, Python, Tcl, Perl, Siemens Tessent, Palladium, ZeBu, Veloce

AI focus

Use modern AI tools for DFT report review, ATPG and coverage analysis, regression triage, documentation, workflow automation, and agentic engineering assistance; the role supports development of AI inference accelerators.