Positron
ASIC Physical Design Engineer, Senior
$200K–$300K
Remote (United States) · Remote · Senior · Full-time · Posted Sep 9, 2026
- Experience
- 5–8 years.
- Visa sponsorship
- Candidates must be currently authorized to work in the U.S.; no new visa sponsorship is available, but H-1B transfers may be facilitated for eligible candidates.
About the job
Implements and closes physical design for AI accelerator ASIC blocks, from floorplanning through tapeout, while contributing to implementation methodology and AI-enabled optimization.
What you'll do
- Execute floorplanning, placement, clock-tree synthesis, routing, and timing and power closure for assigned blocks.
- Support signoff activities, including signal integrity, IR/EM, ECOs, DRC, LVS, and tapeout deliverables.
- Contribute to implementation methodology and apply AI-enabled techniques for QoR analysis, congestion and routing prediction, and floorplan optimization.
What they ask for
- 5–8 years of physical design experience spanning floorplanning through tapeout.
- Experience contributing to one or more advanced-node tapeouts.
- Strong proficiency in Innovus and/or ICC2 implementation flows.
- Working knowledge of physical implementation and experience supporting timing and power signoff.
Nice to have
- Experience with AI accelerator design.
- Familiarity with large SRAM arrays; experience with SerDes, LPDDR, chiplet architectures, or 2.5D advanced packaging.
Pay
$200,000 – $300,000 USD base salary
Tools
Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk, Calibre
AI focus
Apply AI-enabled techniques for automated QoR analysis, congestion prediction, routing prediction, and floorplan optimization.
Model-written summary · the original posting is authoritative