Drimva

Positron

Director of ASIC Design

$200K–$350K

Austin, TX · On-site · Director · Full-time · Posted Aug 1, 2026

Experience
12+ years in ASIC development, including at least 5 years in a leadership role.
Education
Degree in Electrical Engineering, Computer Engineering, or a related field.
Visa sponsorship
Candidates must be currently authorized to work in the U.S.; no new visa sponsorship is available, but H-1B transfers may be facilitated for eligible candidates.

About the job

Leads the design, verification, and delivery of high-performance AI inference ASICs, from architecture through tape-out and production.

What you'll do

  • Lead ASIC architecture, RTL, physical design, verification, and validation across the chip development lifecycle.
  • Drive COT tape-out, first-silicon validation, and production ramp-up; manage foundry, IP vendor, and EDA provider relationships.
  • Build and mentor the ASIC team and collaborate with software and prototyping teams on hardware/software co-design.

What they ask for

  • Degree in Electrical Engineering, Computer Engineering, or a related field.
  • 12+ years of ASIC development experience, including at least 5 years in a leadership role.
  • Track record delivering multiple ASIC/COT projects from concept to mass production.
  • Experience with AI accelerators, HPC, or data center chip designs; expertise in digital design, RTL (Verilog/SystemVerilog), low-power design, and memory subsystem optimization.

Nice to have

  • AI/ML accelerator or custom AI silicon design; successful tape-out on 7nm, 5nm, and/or 3nm COT designs.
  • Experience deploying a Cadence or Synopsys EDA methodology; familiarity with chiplets, heterogeneous computing, external memory/IP integration, or RISC-V.

Pay

$200,000 – $350,000 USD base salary

Tools

Verilog, SystemVerilog, Cadence, Synopsys, Mentor Graphics

AI focus

Leads development of AI inference hardware and defines ASIC architecture and roadmap aligned with AI workloads.

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 6, 2026 (UTC)