Positron
Mid-End ASIC Engineer, Senior
$190K–$280K
Hybrid (Austin, Texas, US) · Hybrid · Senior · Full-time · Posted Jul 31, 2026
- Experience
- 12+ years of ASIC implementation experience, including multiple successful tapeouts.
- Visa sponsorship
- Candidates must be currently authorized to work in the U.S.; no new visa sponsorship is available, but H-1B transfers may be facilitated for eligible candidates.
About the job
Owns synthesis methodology, timing closure, and implementation readiness for ASIC designs powering AI inference accelerators.
What you'll do
- Develop and lead synthesis flows, constraints, and signoff criteria across ASIC generations.
- Drive logical timing closure and physical-aware optimization in collaboration with RTL, architecture, and backend teams.
- Lead technical reviews with external implementation partners and apply AI to engineering analysis and automation.
What they ask for
- Expert-level synthesis methodology and flow development, including Cadence Genus and/or Synopsys Design Compiler.
- Deep timing-closure expertise, strong SDC/MMMC knowledge, and experience with multi-million-gate designs.
- Hands-on experience with advanced process nodes at 5nm and below; strong Tcl and Python scripting ability.
- Solid grasp of RTL design principles and implementation-friendly coding practices.
Nice to have
- Experience with AI accelerators, CPUs, or GPUs; familiarity with LPDDR, PCIe, or SerDes.
- Exposure to chiplet-based architectures and multi-clock SoC designs.
Pay
$190,000 – $280,000 USD base salary
Tools
Cadence Genus, Synopsys Design Compiler, SDC, MMMC, Tcl, Python, LPDDR, PCIe
AI focus
Apply AI to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.
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