Positron
Physical Design Engineer - Synth, Senior
$200K–$300K
Remote (United States) · Remote · Senior · Full-time · Posted Sep 29, 2026
- Experience
- 8+ years of ASIC implementation experience, including at least two successful tapeouts.
- Visa sponsorship
- Candidates must currently be authorized to work in the U.S.; no new visa sponsorship, but H-1B transfers may be facilitated for eligible candidates.
About the job
Own synthesis, timing closure, and physical-aware optimization for ASIC partitions, delivering implementation-ready netlists and improving synthesis methodology for AI accelerators.
What you'll do
- Execute synthesis, develop constraints, and improve synthesis flows and netlist quality.
- Drive timing closure and physical-aware optimization with RTL, architecture, and backend teams.
- Apply AI tools to timing analysis, QoR regression, constraint generation, debugging, report analysis, documentation, and engineering automation.
What they ask for
- Strong hands-on proficiency in synthesis and flow development; deep working knowledge of Cadence Genus and/or Synopsys Design Compiler.
- Proven timing closure experience on complex, multi-million-gate designs; strong SDC and MMMC expertise.
- Solid grasp of RTL design principles and implementation-friendly coding practices.
- Strong Tcl and Python scripting ability for automation and flow development.
Nice to have
- Experience with AI accelerators, CPUs, or GPUs; experience at 5nm and below.
- Familiarity with LPDDR, PCIe, or SerDes; exposure to chiplet-based architectures and multi-clock SoCs; mentoring or subsystem leadership experience.
Pay
$200,000 – $300,000 USD base salary
Tools
Cadence Genus, Synopsys Design Compiler, SDC, MMMC, Tcl, Python, LPDDR, PCIe
AI focus
Apply AI tools to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.
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