Quadric
RTL Intern
Burlingame, CA (HQ) · On-site · Internship · Posted Oct 23, 2026
- Education
- Currently pursuing a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
- Visa sponsorship
- Quadric participates in E-Verify to confirm employment eligibility for U.S.-based roles.
About the job
Supports Quadric’s SoC design team with subsystem development, third-party IP integration, and power, performance, and area optimization for its GPNPU platform.
What you'll do
- Help design and integrate SoC-level subsystems and document architecture and application requirements.
- Assist with SoC-level PPA analysis and optimization, including exposure to low-power design and timing closure.
- Collaborate with SoC architects and designers on integration requirements and communicate findings and blockers.
What they ask for
- Currently pursuing a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
- Familiarity with SoC/ASIC front-end design concepts.
- Proficient in SystemVerilog or Verilog.
- Problem-solving, debugging, collaboration, and clear technical communication skills.
Nice to have
- Coursework or project experience with computer architecture, low-power design, or RTL design; exposure to logic synthesis, FPGA design, or performance modeling.
- Scripting experience with Python and use of LLMs.
Pay
$50-57/hr USD, hourly salary
Tools
SystemVerilog, Verilog, NoC, PCIe/UCIe, DDR, Python, LLMs
AI focus
The role supports SoC design for Quadric’s GPNPU platform, which enables neural network inference and conventional C++ code on a programmable architecture.
Model-written summary · the original posting is authoritative