Qualcomm
3D Memory Chip Architect and Design, Principal Engineer
$200K–$300K
San Diego, California · On-site · Principal · Full-time · Posted Sep 17, 2026
- Experience
- 8+ years with a bachelor’s degree, 7+ years with a master’s degree, or 6+ years with a PhD in ASIC design, verification, validation, integration, or related work.
- Education
- Bachelor's, Master's, or PhD in Science, Engineering, or a related field.
About the job
Architects and optimizes 3D memory and near-memory computing systems, balancing performance, power, thermal, area, and integration constraints for AI, compute, mobile, and XR workloads.
What you'll do
- Develop and validate 3D memory organization, performance, power, yield, and power-distribution models.
- Design high-bandwidth fabrics and simulate or emulate 3D memory system performance across workloads.
- Floorplan 3D memory chips and design memory-array control structures within manufacturing, testability, and performance constraints.
What they ask for
- Bachelor’s degree in Science, Engineering, or related field and 8+ years of relevant experience; or Master’s and 7+ years; or PhD and 6+ years.
- Knowledge of memory bank organization, signaling, buses, IO and compute fabrics, advanced packaging, and 3D integration.
- Knowledge of chip connection fabrics such as UCIe, UAL, LPDDR, HBM3/4, and PCIe.
Nice to have
- Experience in RTL, circuit and system design, SoC architecture, DRAM/FLASH architecture, or memory circuit design.
- Experience with programming or scripting languages, Verilog models, EDA tools, Matlab, and Phyton.
Pay
$200,000.00 - $300,000.00 (pay range; salary/base pay)
Tools
UCIe, UAL, LPDDR, HBM3/4, PCIe, RTL, Verilog, Matlab
AI focus
Architects and evaluates memory-centric computing systems and 3D memory performance across AI workloads.
Model-written summary · the original posting is authoritative