Qualcomm
Analog/Mixed Signal ASIC Design Engineer
$146K–$218K
San Diego, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- Minimum qualifications specify alternatives: bachelor's plus 2+ years of analog or mixed-signal IC design and 4+ years of ASIC design, verification, or related work; master's plus 4+ years of ASIC design, verification, or related work; or PhD plus 2+ years of ASIC design, verification, or related work. Also requires 2+ years using one or more design tools.
- Education
- Bachelor’s, master’s, or PhD in Electrical Engineering; master’s and PhD alternatives allow a related field.
About the job
Designs and delivers high-performance, low-power mixed-signal IP for Qualcomm SOCs and RF transceivers, from architecture and circuit design through verification, bring-up, and production support.
What you'll do
- Define IP architecture and analog/digital design partitioning, and create schematics.
- Run circuit simulations and collaborate with layout and digital teams on implementation, verification, and IP delivery.
- Support post-silicon verification, bring-up, debug, and production with product test teams.
What they ask for
- Bachelor’s in Electrical Engineering plus 2+ years of analog or mixed-signal integrated circuit design in nanometer planar CMOS or FinFET and 4+ years of ASIC design, verification, or related work experience; OR a master’s in Electrical Engineering or related field and 4+ years of ASIC design, verification, or related work experience; OR a PhD in Electrical Engineering or related field and 2+ years of ASIC design, verification, or related work experience.
- 2+ years of experience using one or more design tools (e.g., CADENCE, SPICE, MATLAB, and/or Verilog/VHDL).
- Demonstrated interest in analog circuit design through coursework and/or work experience.
- Experience with ASIC design tools such as Cadence Virtuoso.
Nice to have
- Several years of industry experience in analog integrated circuit/system design or mixed-signal IP design.
- Familiarity with Matlab and Python; understanding of mixed-signal architecture, system integration, yield, production challenges, and sampled-domain signal processing.
Pay
$145,600.00 - $218,400.00 (base salary)
Tools
Cadence Virtuoso, CADENCE, SPICE, MATLAB, Verilog/VHDL, Matlab, Python
AI focus
The IPs support products targeted for AI/ML applications; no AI development work is specified.
Model-written summary · the original posting is authoritative