Qualcomm
Analog Mixed Signal/Power Management Design Engineer (Sr up to Staff)
$122K–$183K
San Diego, California · On-site · Staff · Full-time · Posted Oct 27, 2026
- Experience
- Minimum qualifications specify 2+ years of experience as detailed above; preferred qualification specifies 1+ year interacting with senior leadership.
- Education
- Bachelor's degree in Electrical Engineering, master's degree in Electrical Engineering or related field, or PhD in Electrical Engineering or related field.
About the job
Designs and verifies CMOS mixed-signal and power-management circuit blocks, from architecture and simulation through layout oversight, silicon evaluation, and testing.
What you'll do
- Define architectures and circuit specifications; design, simulate, and verify analog/mixed-signal blocks against power, performance, and functionality targets.
- Oversee block-level layout and silicon evaluation; design tests and analyze bench/ATE results to identify and resolve issues.
- Document designs, contribute to design reviews and new initiatives, and consult with users and vendors on implementation.
What they ask for
- Bachelor's degree in Electrical Engineering plus 2+ years of analog or mixed-signal integrated circuit design in nanometer planar CMOS or FinFET and 2+ years of ASIC design, verification, or related work experience; OR master's degree in Electrical Engineering or related field plus 2+ years of ASIC design, verification, or related work experience; OR PhD in Electrical Engineering or related field.
- 2+ years of experience using one or more design tools, such as CADENCE, SPICE, MATLAB, and/or Verilog/VHDL.
Nice to have
- Experience in analog/mixed-signal integrated CMOS circuit design in a relevant area, such as VCO, PLL, and DLL design; Audio CODEC and Class D Audio amplifier design; data converters; or Buck/Boost regulators.
- 1+ year of work experience in a role requiring interaction with senior leadership.
Pay
$121,800.00 - $182,600.00 USD base salary
Tools
CMOS, FinFET, CADENCE, SPICE, MATLAB, Verilog/VHDL, Cadence ADE, MathWorks MATLAB
Model-written summary · the original posting is authoritative