Qualcomm
ASIC Design Engineer (Hardware Security)
$146K–$218K
San Diego, California +1 · On-site · Full-time · Posted Sep 17, 2026
- Location
- San Diego, California
Santa Clara, California - Experience
- 6+ years with a bachelor's degree; 5+ years with a master's degree; 4+ years with a PhD. The posting also lists 6+ years of ASIC design experience.
- Education
- Bachelor's degree in Science, Engineering, or a related field; master's or PhD preferred.
About the job
Designs and develops ASIC hardware security solutions for Snapdragon chipsets, contributing across architecture, implementation, validation, and silicon testing.
What you'll do
- Work across the hardware product creation flow, including architecture, microarchitecture, RTL design, synthesis, timing closure, layout, and silicon testing.
- Collaborate with cross-functional teams on hardware security solutions, countermeasures, and techniques.
- Contribute to design, validation, IP development, and integration activities.
What they ask for
- Experience with ASIC design flow, including Verilog/SystemVerilog RTL design, clock domain crossings, DFT, synthesis, and timing closure.
- Knowledge of bus protocols, clocks/resets, and debug concepts.
- Strong problem-solving, communication, and teamwork skills; able to work with minimum supervision.
Nice to have
- Experience with microcontroller CPUs, buses (AHB/AXI/others), peripherals, system-level architecture, IP integration, or silicon test.
- Experience in hardware security, verification, modeling, or test planning.
Pay
$145,600.00 - $218,400.00 USD (pay range; salary/base pay)
Tools
ASIC, Verilog, SystemVerilog, AHB, AXI, DFT, Root of Trust, RNG
Model-written summary · the original posting is authoritative