Qualcomm
ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems
$101K–$152K
San Diego, California · On-site · Full-time · Posted Oct 22, 2026
- Experience
- 0-4+ years of industry experience or relevant academic experience in ASIC/SoC design.
- Education
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Designs and validates RTL for SoC interconnect, cache, memory subsystem, and DDR controller components, supporting integration and silicon delivery.
What you'll do
- Define microarchitecture and design specifications; implement and validate RTL for complex SoC subsystems.
- Optimize designs for performance, power, area, timing, and scalability, and support verification, synthesis, timing closure, and physical design.
- Integrate and debug systems, resolve pre- and post-silicon issues, and collaborate across engineering teams to deliver production silicon.
What they ask for
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience or coursework in Verilog and/or SystemVerilog RTL design, computer architecture, ASIC design methodologies, and digital logic design.
- Experience or coursework in C, C++, and/or Python programming.
- Strong analytical and problem-solving skills; excellent communication and collaboration skills.
Nice to have
- Knowledge or experience in SoC interconnects, cache and memory subsystems, DDR/LPDDR controllers, processor architectures, or related RTL design.
- Knowledge or experience in low-power design, functional verification, Synopsys synthesis tools, ASIC implementation, timing closure, physical design, or silicon debug.
Pay
$101,400.00 - $152,200.00 (base salary)
Tools
Verilog, SystemVerilog, C, C++, Python, Synopsys
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