Qualcomm
ASIC Design Verification Engineer (Santa Clara, CA)
$134K–$202K
Santa Clara, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- At least 3 years of design verification experience is stated in the qualifications. Minimum qualifications also specify: bachelor's degree and 2+ years of related work experience, or master's degree and 1+ year, or a PhD.
- Education
- Bachelor's or master's degree in Science, Engineering, or a related field, or PhD in those fields.
About the job
Verifies digital power IP and SoC designs across the pre-silicon lifecycle through tape-out and post-silicon support.
What you'll do
- Develop verification plans, testbenches, coverage, assertions, and formal property checks.
- Apply power-aware UPF verification flows and methodologies.
- Develop automation to improve verification efficiency.
What they ask for
- 3+ years of design verification experience using UVM or assertion-based verification technologies.
- Experience verifying complex SoCs or SoC subsystems.
- Experience with cache and DDR memory protocol verification.
- Experience using memory verification VIPs.
Nice to have
- Exposure to DDR PHY, firmware or driver development using C++, and multiple tape-outs through post-silicon debug.
- Exposure to formal verification, PASIM simulations, and performance and power verification.
Pay
$134,500.00 - $201,700.00 USD base salary
Tools
UVM, SystemVerilog, C++, Python, DDR, CACHE, SOC, UPF
Model-written summary · the original posting is authoritative