Qualcomm
ASIC Design Verification Engineer (Santa Clara, CA)
$113K–$170K
Santa Clara, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- Minimum 3 years of design verification experience.
- Education
- Bachelor's degree in Science, Engineering, or related field.
About the job
Verifies digital power IP and related SoC designs from system-level planning through tape-out and post-silicon support.
What you'll do
- Develop pre-silicon test plans, testbenches, coverage, assertions, and formal verification.
- Deploy power-aware UPF verification flows and methodologies.
- Develop automation to improve verification efficiency.
What they ask for
- At least 3 years of design verification experience using UVM and assertion-based verification technologies.
- Experience verifying complex SoCs or SoC subsystems.
- Experience with cache and DDR memory protocol verification.
- Bachelor's degree in Science, Engineering, or a related field.
Nice to have
- Exposure to DDR PHY, firmware/driver development using C++, multiple tape-outs, formal verification, PASIM simulations, or performance and power verification.
- Experience using memory verification VIPs.
Pay
$113,000.00 - $169,600.00 USD (base salary)
Tools
UVM, system verilog, assertion, C++, python, DDR, CACHE, SOC
Model-written summary · the original posting is authoritative