Qualcomm
ASIC Design Verification Engineer (Security Group) - Sr Staff
$190K–$285K
Santa Clara, California · On-site · Senior Staff · Full-time · Posted Oct 23, 2026
- Experience
- General Summary asks for 10+ years in SOC-level verification; minimum qualifications specify 6+ years with a bachelor's degree, 5+ with a master's degree, or 4+ with a PhD.
- Education
- Bachelor's, master's, or PhD degree in Science, Engineering, or related field.
About the job
Verifies secure ASIC subsystems from architecture through bring-up and regression, ensuring functional correctness and coverage for product readiness.
What you'll do
- Develop verification plans, methodologies, testbenches, stimulus, checkers, assertions, and coverage for subsystem designs.
- Bring up verification environments, run regressions, debug failures, and track bugs and coverage progress.
- Collaborate with architects and cross-functional teams on requirements, design trade-offs, technical documentation, and review guidance for team members.
What they ask for
- Solid understanding of SystemVerilog and UVM concepts.
- Experience with SOC-level verification and debugging ARM-based or RISC-V-based processors; understanding of APB/AHB/AXI protocols.
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience; OR Master's degree and 5+ years; OR PhD and 4+ years.
- Basic understanding of UNIX commands and Python/Perl scripting.
Nice to have
- Experience with cryptographic algorithms.
- Knowledge of APB/AXI/SPI protocols, clock domains, memory organization, fault tolerance, and error detection/correction; experience with formal verification, silicon bring-up, test plans, or portable testbenches.
Pay
$190,200.00 - $285,400.00 USD (pay range; salary)
Tools
SystemVerilog, UVM, Synopsys VCS/Verdi, Makefile automation, Python, Perl, UNIX, APB/AHB/AXI
Model-written summary · the original posting is authoritative