Qualcomm
ASIC DTCO, Timing and Technology Engineer
$146K–$218K
San Diego, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- 4+ years with a bachelor's degree, 3+ years with a master's degree, or 2+ years with a PhD in ASIC design, verification, validation, integration, or related work.
- Education
- Bachelor's, master's, or PhD in Science, Engineering, or related field.
About the job
Evaluates and improves process-technology entitlement, power, performance, timing, and cost for SoC blocks and systems, and supports advanced-node technology bring-up.
What you'll do
- Run Spice simulations and static timing analysis sign-off for power and performance validation.
- Analyze and implement block-level PPA for hard macros using RTL-to-GDS flows.
- Collaborate with foundry, EDA, CAD, and IP teams to optimize Fmax, PPAY, cost, and design convergence.
What they ask for
- Programming skills in Python, Perl, TCL, Unix shell, and C/C++.
- Bachelor's degree in Science, Engineering, or related field and 4+ years of relevant experience; or master's degree and 3+ years; or PhD and 2+ years.
Nice to have
- ML modeling experience.
Pay
$145,600.00 - $218,400.00 USD base salary
Tools
Hspice, Finesim, PrimeSim, AFS, Spectre, PT/PT-SI, Tempus, Python
Model-written summary · the original posting is authoritative