Qualcomm
ASIC Methodology Engineer
$160K–$239K
Santa Clara, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- The role summary asks for 1–2 years of relevant ASIC/VLSI design tools and flows experience. Minimum qualifications also state: bachelor's degree plus 4+ years, master's degree plus 3+ years, or PhD plus 2+ years of ASIC-related work experience.
- Education
- M.S./Ph.D. in Electrical Engineering or Computer Science; minimum qualifications also list a bachelor's, master's, or PhD in Science, Engineering, or a related field.
About the job
Develop and enable a design analytics platform and ASIC methodology that supports power, performance, area, and product quality across core and SOC teams.
What you'll do
- Work with core and SOC teams to enable a state-of-the-art design analytics platform.
- Contribute to ASIC design methodology and analysis using timing tools and design flows.
What they ask for
- Strong programming skills in Python.
- Hands-on experience with static timing analysis (STA) tools.
- Problem-solving and analytical mindset.
- A relevant degree and ASIC/VLSI design tools and flows experience; requirements list differing experience thresholds by degree.
Nice to have
- Familiarity with GenAI models and real-world applications, and experience developing agentic AI systems.
- Experience with version control tools, place & route tools, and the ASIC RTL-GDSII design flow.
Pay
$159,600.00 - $239,400.00 USD base salary
Tools
Python, PrimeTime, Tempus, GenAI, LLMs, GPT, Liama, Perforce, Git
AI focus
Preferred experience includes applying GenAI models such as LLMs to real-world solutions and designing and developing agentic AI systems.
Model-written summary · the original posting is authoritative