Qualcomm
ASIC/RTL Design Engineer for High-speed Interfaces
$146K–$218K
San Diego, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- 7+ years in RTL and ASIC design; 5+ years of hands-on mixed-signal IP micro-architecture and digital design. The posting also lists baseline alternatives: bachelor's plus 4+ years, master's plus 3+ years, or PhD plus 2+ years in ASIC design, verification, validation, integration, or related work.
- Education
- Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
About the job
Architects, designs, implements, and validates high-speed mixed-signal interface IPs, including SerDes, DDR, and die-to-die interconnects, across the ASIC design flow.
What you'll do
- Define micro-architecture and implement RTL for high-speed interface IPs, optimizing power, performance, and area.
- Use ASIC tools for design analysis and verification, including DFT, synthesis, formal verification, and timing analysis.
- Collaborate on verification, physical design, SoC integration, and pre- and post-silicon debug.
What they ask for
- Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 7+ years of experience in RTL and ASIC design.
- 5+ years of hands-on micro-architecture and digital design for mixed-signal IPs, such as SerDes, DDR PHY, PLLs, DACs, ADCs, and sensors.
- Proficiency with front-end ASIC design tools, including VCS, Fusion Compiler, PrimeTime, Power Compiler (PTPX), DFT Compiler, and Spyglass.
Nice to have
- Ph.D. in Electrical Engineering with 5+ years of industry experience in high-speed digital circuit design.
- Low-power digital design; computer architecture, digital signal processing, and algorithm development; or Python/Perl automation scripting.
Pay
$145,600.00 - $218,400.00 USD (pay range; salary, base pay)
Tools
VCS, Fusion Compiler, PrimeTime, Power Compiler (PTPX), DFT Compiler, Spyglass, Python, Perl
AI focus
Designs interface IPs for integration across Qualcomm products, including AI; no specific AI development work is stated.
Model-written summary · the original posting is authoritative